This disclosure relates generally to improving signal quality by recovering data from a serial data signal received by circuitry, and more particularly to adapting a transmitter sending the serial data signal based on receiving the serial data signal.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.
Communicating data between components of a system using high speed serial data signals is of increasing interest and importance to electronic system designers and users. The high speed serial data signals may convey data from one programmable logic integrated circuit (IC) in a system to another programmable logic IC in the system or between components of the same IC. The system may include a single computing device or multiple computing devices connected via wire or wirelessly (e.g., using the Internet).
One problem when using high speed serial data signals is that the signals may be subject to loss of clarity or fidelity when propagating through a medium used to transmit the signals. The loss of fidelity (which may be characterized as signal degradation, attenuation, loss, noise, inter-symbol-interference (ISI), and the like) tends to become more significant as a data rate (e.g., serial bit rate) of the signal increases. The higher the data rate of the serial data signal, the more the signal/transmission degrades. Signal degradation (e.g., as described above from a programmable logic IC transmitting that signal through a transmission medium to another programmable logic IC receiving the signal) increases the difficulty of the receiving IC to correctly interpret the data in the received signal.
To compensate for at least some of the signal degradation that may cause or contribute to receiver data interpretation errors, the receiving IC may be equipped with equalization and/or adaptation circuitry for processing the received high speed serial data signal (e.g., prior to any attempt to recover data information from that signal in more downstream circuitry). In particular, specialized adaptive recovery circuits may compensate for signal degradation due to ISI. For example, Forward Equalization (e.g., R-C/FFE) circuitry and/or Decision Feedback Equalizer (DFE) circuitry may be used at the receiver end. DFE is generally regarded as the most effective at removing post-cursor ISI. A DFE may have multiple “taps,” each of which may include a circuit for multiplying a respective earlier (previously received) data bit value (e.g., the kth data bit value prior to a current bit) of an incoming signal by a respective tap coefficient Ck and combining the resulting products with the incoming signal for the current bit. The DFE may determine effective sets of DFE tap coefficient values such that an acceptably low bit error rate is achieved by the receiving IC in recovering data from the received serial data signal.
A DFE may include a summation node that uses the coefficient value to filter the received signal. The summation node may be a partial summation node, which may use a data slicing level (dLev) to “slice” or predict an error value representative of errors in a received serial data signal caused by ISI. (The value dLev may be used to determine whether a symbol in a received signal is a logic one or a logic zero.) In general, dLev is a static setting (e.g., set via configuration bits) in a programmable logic IC. This static setting may limit the quality of the results of signal conditioning adaptive recovery circuitry and may also make performance prone to environmental variations, such as variations in temperature, voltage, or noise. Although dLev adaptation may be used with full response/full rate DFE structures, the timing of these type of DFE structures may not be closed for high speeds such as 28 Gbps for a 20 nanometer process node. Moreover, using half rate DFE structures may require an excessive number of high speed multipliers and sense amplifiers (that may cause excessive loading on the summation node, increase intrinsic kickback noise generated on the summation node, and increase cost and area required for the receiver), as well as high speed multiplexers.
Furthermore, the summation node may employ a defined signal amplitude level for the received signal. The dynamic range of the received signal may be undefined, and may include transmitter output voltage variations, channel loss characteristics that cause amplitude variation, and amplitude uncertainty due to the frequency response of any receiver buffers used to receive the incoming signal.
As used herein, a bit is a binary digit, typically having a value of either 1 or 0. Also as used herein, the singular term “serial data signal” may be used as a generic term for both single-ended and differential serial data signals (even though a differential serial data signal includes two complementary signal constituents).